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MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
14 years 3 months ago
Tradeoffs in designing accelerator architectures for visual computing
Visualization, interaction, and simulation (VIS) constitute a class of applications that is growing in importance. This class includes applications such as graphics rendering, vid...
Aqeel Mahesri, Daniel R. Johnson, Neal C. Crago, S...
MICRO
2008
IEEE
113views Hardware» more  MICRO 2008»
14 years 3 months ago
From SODA to scotch: The evolution of a wireless baseband processor
With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly chan...
Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, ...
SASP
2008
IEEE
162views Hardware» more  SASP 2008»
14 years 3 months ago
Accelerating Compute-Intensive Applications with GPUs and FPGAs
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadr...
WCNC
2008
IEEE
14 years 3 months ago
Performance Improvement for Multichannel HARQ Protocol in Next Generation WiMAX System
Hybrid automatic repeat-request (HARQ) is critical to an IEEE 802.16e OFDMA network, as it can significantly improve the reliability of wireless link. However, as revealed by our...
Zhifeng Tao, Anfei Li, Jinyun Zhang, Toshiyuki Kuz...
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
14 years 3 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...
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