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HPCA
2009
IEEE
14 years 9 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
HPCA
2009
IEEE
14 years 9 months ago
Criticality-based optimizations for efficient load processing
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
Samantika Subramaniam, Anne Bracy, Hong Wang 0003,...
VLSID
2006
IEEE
121views VLSI» more  VLSID 2006»
14 years 9 months ago
An Integrated Approach for Combining BDD and SAT Provers
Many formal verification tools today are based on Boolean proof techniques. The two most powerful approaches in this context are Binary Decision Diagrams (BDDs) and methods based ...
Rolf Drechsler, Görschwin Fey, Sebastian Kind...
HPCA
2008
IEEE
14 years 9 months ago
Cluster-level feedback power control for performance optimization
Power control is becoming a key challenge for effectively operating a modern data center. In addition to reducing operating costs, precisely controlling power consumption is an es...
Xiaorui Wang, Ming Chen
HPCA
2008
IEEE
14 years 9 months ago
Fabric convergence implications on systems architecture
Converged fabrics that support data, storage, and cluster networking in a unified fashion are desirable for their cost and manageability advantages. Recent trends towards higher-b...
Kevin Leigh, Parthasarathy Ranganathan, Jaspal Sub...