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» Parallelizing time with polynomial circuits
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ASPDAC
2004
ACM
75views Hardware» more  ASPDAC 2004»
14 years 1 months ago
A thread partitioning algorithm in low power high-level synthesis
This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe pa...
Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Ta...
ISCAS
2006
IEEE
82views Hardware» more  ISCAS 2006»
14 years 1 months ago
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing
– This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are ...
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
IPPS
2003
IEEE
14 years 1 months ago
Importance of SIMD Computation Reconsidered
In this paper, SIMD and MIMD solutions for the realtime database management problem of air traffic control are compared. A real-time database system is highly constrained in a mul...
Will C. Meilander, Johnnie W. Baker, Mingxian Jin
IPPS
2003
IEEE
14 years 1 months ago
Task Graph Scheduling Using Timed Automata
In this paper we develop a methodology for treating the problem of scheduling partially-ordered tasks on parallel machines. Our framework is based on the timed automaton model, or...
Yasmina Abdeddaïm, Abdelkarim Kerbaa, Oded Ma...
HPCA
2009
IEEE
14 years 2 months ago
Reconciling specialization and flexibility through compound circuits
While parallelism and multi-cores are receiving much attention as a major scalability path, customization is another, orthogonal and complementary, scalability path which can targ...
Sami Yehia, Sylvain Girbal, Hugues Berry, Olivier ...