A thread partitioning algorithm in low power high-level synthesis

This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe parallel behaving circuit blocks(threads) ezplicitly. First it focuses on a local register file RF in a thread. It partitions a thread into two sub-threads, one of which has RF and the other does not have RF. The partitioned sub-threads need to be synchronized with each other to keep the data dependency of the original thread. Since the partitioned sub-threads have waiting time for synchronization, gated clocks can be applied to each subthread. Then we can synthesize a low power circuit urith a low area overhead, compared to the original circuit. Ezperimental results demonstrate effectiveness and eficiency of the algorithm.

• Type: Conference
• Year: 2004
• Where: ASPDAC
• Authors: Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
• Keywords: ASPDAC 2004, Low Power, Parallel Behaving Circuit, Thread Partitioning Algorithm