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» Parameterized Function Evaluation for FPGAs
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DATE
2010
IEEE
166views Hardware» more  DATE 2010»
14 years 4 months ago
A special-purpose compiler for look-up table and code generation for function evaluation
Abstract—Elementary functions are extensively used in computer graphics, signal and image processing, and communication systems. This paper presents a special-purpose compiler th...
Yuanrui Zhang, Lanping Deng, Praveen Yedlapalli, S...
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
14 years 4 months ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna
CASES
2005
ACM
14 years 26 days ago
Automating custom-precision function evaluation for embedded processors
Due to resource and power constraints, embedded processors often cannot afford dedicated floating-point units. For instance, the IBM PowerPC processor embedded in Xilinx Virtex-...
Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne ...
DAC
2002
ACM
14 years 12 months ago
IP delivery for FPGAs using Applets and JHDL
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
Michael J. Wirthlin, Brian McMurtrey
ICES
2005
Springer
195views Hardware» more  ICES 2005»
14 years 4 months ago
Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs
A specialized architecture was developed and evaluated to evolve relatively large sorting networks in an ordinary FPGA. Genetic unit and fitness function are also implemented on t...
Jan Korenek, Lukás Sekanina