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» Parameterized Function Evaluation for FPGAs
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RECONFIG
2008
IEEE
268views VLSI» more  RECONFIG 2008»
14 years 4 months ago
Parametric, Secure and Compact Implementation of RSA on FPGA
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
Ersin Oksuzoglu, Erkay Savas
DAC
2012
ACM
12 years 7 days ago
Chisel: constructing hardware in a Scala embedded language
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific h...
Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup ...
EH
2004
IEEE
117views Hardware» more  EH 2004»
14 years 1 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
EVOW
2007
Springer
14 years 1 months ago
Dinucleotide Step Parameterization of Pre-miRNAs Using Multi-objective Evolutionary Algorithms
MicroRNAs (miRNAs) form a large functional family of small noncoding RNAs and play an important role as posttranscriptional regulators, by repressing the translation of mRNAs. Rece...
Jin-Wu Nam, In-Hee Lee, Kyu Baek Hwang, Seong-Bae ...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 6 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He