In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameter...
In this paper we propose a new design methodology targeted for core-based designs using parameterized macrocells (PMC’s). This methodology provides the flexibility for instance...
Makram M. Mansour, Mohammad M. Mansour, Amit Mehro...
Abstract-- Preventing silicon chips from negative, even disastrous thermal hazards has become increasingly challenging these days; considering thermal effects early in the design c...
Wei Huang, Karthik Sankaranarayanan, Kevin Skadron...
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...
Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-...