149 search results - page 11 / 30 » Parametric Fault Simulation and Test Vector Generation |
DAC
2000
ACM
13 years 11 months ago
2000
ACM
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
ATS
2009
IEEE
14 years 2 months ago
2009
IEEE
—Measuring the steady state leakage current (IDDQ) is very successful in detecting faults not discovered by standard fault models. But vector dependencies of IDDQ decrease the re...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract: With the increasing complexity of memory behavior, attempts are being made to come up with a methodical approach that employs electrical simulation to tackle the memory t...
VTS
2002
IEEE
14 years 8 days ago
2002
IEEE
High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Inp...
ET
2010
13 years 4 months ago
2010
This work justifies several quantum gate level fault models and discusses the causal error mechanisms thwarting correct function. A quantum adaptation of the classical test set gen...