149 search results - page 16 / 30 » Parametric Fault Simulation and Test Vector Generation |
ICCV
2011
IEEE
12 years 7 months ago
2011
IEEE
3D parametric deformable models have been used to extract volumetric object boundaries and they generate smooth boundary surfaces as results. However, in some segmentation cases, ...
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
This paper presents a new approach for diagnosing stuck-at and short faults in interconnects whose layouts are known. This structural approach exploits dierent graph coloring and ...
VTS
2002
IEEE
14 years 9 days ago
2002
IEEE
This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverag...
MTDT
2003
IEEE
14 years 20 days ago
2003
IEEE
Abstract: The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a ne...
ATS
2000
IEEE
13 years 11 months ago
2000
IEEE
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...