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FOCS
1994
IEEE
14 years 12 days ago
Finding the k Shortest Paths
We describe algorithms for finding the k shortest paths connecting a given pair of vertices in a digraph (allowing cycles). Our algorithms output an implicit representation of the...
David Eppstein
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
14 years 17 days ago
Efficient incremental clock latency scheduling for large circuits
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
Christoph Albrecht
COMPGEOM
1990
ACM
14 years 28 days ago
Minimum-Link Paths Among Obstacles in the Plane
Given a set of nonintersecting polygonal obstacles in the plane, the link distance between two points s and t is the minimum number of edges required to form a polygonal path conn...
Joseph S. B. Mitchell, Günter Rote, Gerhard J...
ESA
2006
Springer
139views Algorithms» more  ESA 2006»
14 years 16 days ago
Stochastic Shortest Paths Via Quasi-convex Maximization
Abstract. We consider the problem of finding shortest paths in a graph with independent randomly distributed edge lengths. Our goal is to maximize the probability that the path len...
Evdokia Nikolova, Jonathan A. Kelner, Matthew Bran...
ERSA
2009
129views Hardware» more  ERSA 2009»
13 years 6 months ago
Data path Configuration Time Reduction for Run-time Reconfigurable Systems
- The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS...
Mahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabe...