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ICCAD
1996
IEEE
86views Hardware» more  ICCAD 1996»
13 years 12 months ago
Tearing based automatic abstraction for CTL model checking
Based Automatic Abstraction for CTL Model Checking Woohyuk Lee Abelardo Pardo Jae-Young Jang Gary Hachtel Fabio Somenzi University of Colorado ECEN Campus Box 425 Boulder, CO, 8030...
Woohyuk Lee, Abelardo Pardo, Jae-Young Jang, Gary ...
ICRA
1994
IEEE
147views Robotics» more  ICRA 1994»
13 years 12 months ago
Provable Strategies for Vision-Guided Exploration in Three Dimensions
An approach is presented for exploring an unknown, arbitrary surface in three-dimensional (3D) space by a mobile robot. The main contributions are (1) an analysis of the capabilit...
Kiriakos N. Kutulakos, Charles R. Dyer, Vladimir J...
ASPDAC
2007
ACM
100views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
CONEXT
2007
ACM
13 years 11 months ago
NetDiagnoser: troubleshooting network unreachabilities using end-to-end probes and routing data
The distributed nature of the Internet makes it difficult for a single service provider to troubleshoot the disruptions experienced by its customers. We propose NetDiagnoser, a tr...
Amogh Dhamdhere, Renata Teixeira, Constantine Dovr...
DELTA
2004
IEEE
13 years 11 months ago
Scan Test of IP Cores in an ATE Environment
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi