112 search results - page 4 / 23 » Path based buffer insertion |
ISQED
2003
IEEE
14 years 26 days ago
2003
IEEE
Scan chain insertion can have large impact on routability, wirelength and timing. We propose a routing-driven and timing-aware methodology for scan insertion with minimum wireleng...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constrai...
DATE
1999
IEEE
13 years 12 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Increasing system complexity and test cost demands new system-level solutions for mixed-signal systems. In this paper, we present a testability analysis and DfT insertion methodol...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...