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DAC
2012
ACM
12 years 1 months ago
A metric for layout-friendly microarchitecture optimization in high-level synthesis
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
Jason Cong, Bin Liu
ACL
2012
12 years 1 months ago
Historical Analysis of Legal Opinions with a Sparse Mixed-Effects Latent Variable Model
We propose a latent variable model to enhance historical analysis of large corpora. This work extends prior work in topic modelling by incorporating metadata, and the interactions...
William Yang Wang, Elijah Mayfield, Suresh Naidu, ...
DATE
2007
IEEE
86views Hardware» more  DATE 2007»
14 years 5 months ago
Reduction of detected acceptable faults for yield improvement via error-tolerance
Error-tolerance is an innovative way to enhance the effective yield of IC products. Previously a test methodology based on error-rate estimation to support error-tolerance was pro...
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
FCCM
2007
IEEE
107views VLSI» more  FCCM 2007»
14 years 5 months ago
Optimizing Logarithmic Arithmetic on FPGAs
This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, ...
Haohuan Fu, Oskar Mencer, Wayne Luk
ML
2010
ACM
151views Machine Learning» more  ML 2010»
13 years 9 months ago
Inductive transfer for learning Bayesian networks
In several domains it is common to have data from different, but closely related problems. For instance, in manufacturing, many products follow the same industrial process but with...
Roger Luis, Luis Enrique Sucar, Eduardo F. Morales