In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
We propose a latent variable model to enhance historical analysis of large corpora. This work extends prior work in topic modelling by incorporating metadata, and the interactions...
William Yang Wang, Elijah Mayfield, Suresh Naidu, ...
Error-tolerance is an innovative way to enhance the effective yield of IC products. Previously a test methodology based on error-rate estimation to support error-tolerance was pro...
This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, ...
In several domains it is common to have data from different, but closely related problems. For instance, in manufacturing, many products follow the same industrial process but with...
Roger Luis, Luis Enrique Sucar, Eduardo F. Morales