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ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
14 years 1 months ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
IPPS
2006
IEEE
14 years 2 months ago
A pattern selection algorithm for multi-pattern scheduling
The multi-pattern scheduling algorithm is designed to schedule a graph onto a coarse-grained reconfigurable architecture, the result of which depends highly on the used patterns....
Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit
TVLSI
2008
151views more  TVLSI 2008»
13 years 8 months ago
Guest Editorial Special Section on Design Verification and Validation
ion levels. The framework also supports the generation of test constraints, which can be satisfied using a constraint solver to generate tests. A compositional verification approac...
I. Harris, D. Pradhan
ICRA
1995
IEEE
125views Robotics» more  ICRA 1995»
13 years 11 months ago
Inductive Generation of Diagnostic Knowledge for Autonomous Assembly
A generic architecture for evolutive supervision of robotized assembly tasks is presented. This architecture , at different levels of abstraction, functions for dispatching action...
Luís Seabra Lopes, Luis M. Camarinha-Matos
HICSS
2000
IEEE
121views Biometrics» more  HICSS 2000»
14 years 15 days ago
Working with Patterns and Code
This paper describes the basis for a suite of tools that let the programmer work in terms of design patterns and source code simultaneously. It first introduces a language for de...
Steven P. Reiss