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ICCD
2003
IEEE
113views Hardware» more  ICCD 2003»
14 years 1 months ago
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nour...
HPCA
2003
IEEE
14 years 8 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
IPCCC
2007
IEEE
14 years 2 months ago
Workload Characterization for News-on-Demand Streaming Services
This paper focuses on design issues for multimedia distribution architectures and the impact workload characteristics have on architecture design. Our contribution is an analysis ...
Frank T. Johnsen, Trude Hafsoe, Carsten Griwodz, P...
ET
2006
154views more  ET 2006»
13 years 7 months ago
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...
Jack Smith, Tian Xia, Charles E. Stroud
FPL
2008
Springer
116views Hardware» more  FPL 2008»
13 years 9 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...