Sciweavers

230 search results - page 39 / 46
» Performance Analysis of Parallel N-Body Codes
Sort
View
CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ICS
2009
Tsinghua U.
14 years 7 days ago
A translation system for enabling data mining applications on GPUs
Modern GPUs offer much computing power at a very modest cost. Even though CUDA and other related recent developments are accelerating the use of GPUs for general purpose applicati...
Wenjing Ma, Gagan Agrawal
EUROPAR
2008
Springer
13 years 9 months ago
Transparent Mobile Middleware Integration for Java and .NET Development Environments
Developing a distributed application for mobile resource constrained devices is a difficult and error-prone task that requires awareness of several system-level details (e.g., faul...
Edgar Marques, Luís Veiga, Paulo Ferreira
ISESE
2005
IEEE
14 years 1 months ago
Empirical study design in the area of high-performance computing (HPC)
The development of High-Performance Computing (HPC) programs is crucial to progress in many fields of scientific endeavor. We have run initial studies of the productivity of HPC d...
Forrest Shull, Jeffrey Carver, Lorin Hochstein, Vi...
ISPASS
2010
IEEE
14 years 2 months ago
Visualizing complex dynamics in many-core accelerator architectures
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...
Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, ...