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CODES
2003
IEEE
14 years 1 months ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
IPPS
2002
IEEE
14 years 18 days ago
System-Level Analysis for MPEG-4 Decoding on a Multi-Processor Architecture
The convergence of TV and new features such as Internet and games, requires a generic media-processing platform, that enables simultaneous execution of very diverse tasks, ranging...
Egbert G. T. Jaspers, Erik B. van der Tol, Peter H...
IPPS
2009
IEEE
14 years 2 months ago
Performance analysis of distributed intrusion detection protocols for mobile group communication systems
Under highly security vulnerable, resource restricted, and dynamically changing mobile ad hoc environments, it is critical to be able to maximize the system lifetime while boundin...
Jin-Hee Cho, Ing-Ray Chen
DATE
2006
IEEE
125views Hardware» more  DATE 2006»
14 years 1 months ago
Formal performance analysis and simulation of UML/SysML models for ESL design
UML2 and SysML try to adopt techniques known from software development to systems engineering. However, the focus has been put on modeling aspects until now and quantitative perfo...
Alexander Viehl, Timo Schönwald, Oliver Bring...
DATE
2010
IEEE
184views Hardware» more  DATE 2010»
14 years 23 days ago
An analytical method for evaluating Network-on-Chip performance
Today, due to the increasing demand for more and more complex applications in the consumer electronic market segment, Systems-on-Chip consist of many processing elements and becom...
Sahar Foroutan, Yvain Thonnart, Richard Hersemeule...