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ISCA
2007
IEEE
192views Hardware» more  ISCA 2007»
15 years 10 months ago
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
The recently released SPEC CPU2006 benchmark suite is expected to be used by computer designers and computer architecture researchers for pre-silicon early design analysis. Partia...
Aashish Phansalkar, Ajay Joshi, Lizy Kurian John
139
Voted
LCTRTS
1998
Springer
15 years 8 months ago
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
Thomas Lundqvist, Per Stenström
CODES
2009
IEEE
15 years 10 months ago
A variation-tolerant scheduler for better than worst-case behavioral synthesis
– There has been a recent shift in design paradigms, with many turning towards yield-driven approaches to synthesize and design systems. A major cause of this shift is the contin...
Jason Cong, Albert Liu, Bin Liu
ESCIENCE
2007
IEEE
15 years 10 months ago
Building a Data Grid for the Australian Nanostructural Analysis Network
: This paper describes the architecture and services developed by the GRANI project for the Australian Nanostructural Analysis Network Organization (NANO). The aim of GRANI was to ...
Brendan Mauger, Jane Hunter, John Drennan, Ashley ...
124
Voted
APSEC
2005
IEEE
15 years 9 months ago
Feature Analysis for Service-Oriented Reengineering
Web Services together with Service-Oriented Architectures (SOA) are playing an important role in the future of distributed computing, significantly impacting software development ...
Feng Chen, Shaoyun Li, William Cheng-Chung Chu