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RTAS
2008
IEEE
14 years 2 months ago
Bounding Worst-Case Response Time for Tasks with Non-Preemptive Regions
Real-time schedulability theory requires a priori knowledge of the worst-case execution time (WCET) of every task in the system. Fundamental to the calculation of WCET is a schedu...
Harini Ramaprasad, Frank Mueller
ECRTS
2005
IEEE
14 years 1 months ago
Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Antonio Martí Campoy, Isabelle Puaut, Angel...
WSC
2007
13 years 10 months ago
Using ontologies for simulation integration
This paper describes the motivations, methods, and solution concepts for the use of ontologies for simulation model integration. Ontological analysis has been shown to be an effec...
Perakath C. Benjamin, Kumar V. Akella, Ajay Verma
DAC
2005
ACM
14 years 8 months ago
Energy optimal speed control of devices with discrete speed sets
We obtain analytically, the energy optimal speed profile of a generic multi-speed device with a discrete set of speeds, to execute a given task within a given time. Current implem...
Ravishankar Rao, Sarma B. K. Vrudhula
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 8 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das