280 search results - page 4 / 56 » Performance Engineering with the UML Profile for Schedulabil... |
ECRTS
2008
IEEE
14 years 3 months ago
2008
IEEE
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
MSR
2011
ACM
12 years 11 months ago
2011
ACM
A good understanding of the impact of different types of bugs on various project aspects is essential to improve software quality research and practice. For instance, we would ex...
ECRTS
2006
IEEE
14 years 2 months ago
2006
IEEE
We study the problem of dynamically scheduling a set of state-feedback control tasks controlling a set of linear plants. We consider an on-line non-preemptive scheduling policy th...
IADIS
2004
13 years 10 months ago
2004
The evolving nature of complex traffic issues of IP (Internet Protocol)-based Telecollaboration (TC) business system technology requires an intuitive understanding for the partici...
EUROSYS
2010
ACM
14 years 26 days ago
2010
ACM
Effective use of CPU data caches is critical to good performance, but poor cache use patterns are often hard to spot using existing execution profiling tools. Typical profilers at...