17 search results - page 1 / 4 » Performance Evaluation of Adaptive Routing Algorithms for ac... |
ASAP
2007
IEEE
13 years 7 months ago
2007
IEEE
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
TCAD
2010
13 years 2 months ago
2010
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
DSD
2006
IEEE
14 years 1 months ago
2006
IEEE
Region concept helps to accommodate cores larger than the tile size in mesh topology NoC architectures. In addition, it offers many new opportunities for NoC design, as well as pr...
LCTRTS
2010
Springer
13 years 5 months ago
2010
Springer
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
CAL
2004
13 years 7 months ago
2004
In this paper we present a methodology to design fault-tolerant routing algorithms for regular direct interconnection networks. It supports fully adaptive routing, does not degrade...