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ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
14 years 1 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
FCCM
2011
IEEE
251views VLSI» more  FCCM 2011»
12 years 11 months ago
A Scalable Multi-FPGA Platform for Complex Networking Applications
Abstract—Ballooning traffic volumes and increasing linkspeeds require ever high compute power to perform complex real-time processing of network packets. FPGAs have already been...
Sascha Mühlbach, Andreas Koch
SIGIR
1995
ACM
13 years 11 months ago
Integrating IR and RDBMS Using Cooperative Indexing
The full integration of information retrieval (IR) features into a database management system (DBMS) has long been recognized as both a significant goal and a challenging undertak...
Samuel DeFazio, Amjad M. Daoud, Lisa Ann Smith, Ja...
JUCS
2006
112views more  JUCS 2006»
13 years 7 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
ICPP
2009
IEEE
14 years 2 months ago
End-to-End Study of Parallel Volume Rendering on the IBM Blue Gene/P
—In addition to their role as simulation engines, modern supercomputers can be harnessed for scientific visualization. Their extensive concurrency, parallel storage systems, and...
Tom Peterka, Hongfeng Yu, Robert B. Ross, Kwan-Liu...