472 search results - page 14 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
JPDC
2007
13 years 7 months ago
2007
The core of current-generation high-performance multiprocessor systems is out-of-order execution processors with aggressive branch prediction. Despite their relatively high branch...
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
With the ongoing advancements in VLSI technology, the performance of an embedded system is determined to a large extend by the communication of data and instructions. This results...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
There are two basic models for the on-chip memory in CMP systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison o...
ISCA
2007
IEEE
13 years 7 months ago
2007
IEEE
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
To maintain coherence in conventional shared-memory multiprocessor systems, processors first check other processors’ caches before obtaining data from memory. This coherence che...