472 search results - page 6 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
HICSS
1999
IEEE
13 years 11 months ago
1999
IEEE
Distributed Shared Memory (DSM) combines the scalability of loosely coupled multicomputer systems with the ease of usability of tightly coupled multiprocessors, and allows transpa...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
IPPS
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper we propose a simple extension to the I/O architecture of scalable multiprocessors that optimizes page swap-outs significantly. More specifically, we propose the use o...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...