472 search results - page 90 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
ISPASS
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
CODES
2009
IEEE
14 years 5 days ago
2009
IEEE
Reconfigurable Processors utilize a reconfigurable fabric (to implement application-specific accelerators) and may perform runtime reconfigurations to exchange the set of deployed...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...