472 search results - page 9 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
HPCA
2007
IEEE
14 years 1 months ago
2007
IEEE
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
TC
1998
13 years 7 months ago
1998
—When parallel programs are executed on multiprocessors with private caches, a set of data may be repeatedly used and modified by different threads. Such data sharing can often r...
EUROPAR
2005
Springer
14 years 1 months ago
2005
Springer
There are two important hurdles that restrict the scalability of directory-based shared-memory multiprocessors: the directory memory overhead and the long L2 miss latencies due to ...
ICPP
1990
IEEE
13 years 11 months ago
1990
IEEE
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...