428 search results - page 43 / 86 » Performance Modelling and Evaluation of Firewall Architectur... |
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
MMM
2007
Springer
14 years 2 months ago
2007
Springer
Abstract. In this paper, we present a generic 3-D modeling for analyzing court-net sports videos, which enables to map points in the real-world coordinates to the image coordinates...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
We present a tool suite for building, simulating, and analyzing the results of hierarchical descriptions of the scheduling policy for modules sharing a bus in real-time applicatio...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
– In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhan...