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ISQED
2008
IEEE
85views Hardware» more  ISQED 2008»
14 years 3 months ago
A Statistic-Based Approach to Testability Analysis
This paper presents a statistic-based approach for evaluating the testability of nodes in combinational circuits. This testability measurement is obtained via Monte Carlo simulati...
Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen
FCCM
2003
IEEE
148views VLSI» more  FCCM 2003»
14 years 2 months ago
A Hardware Gaussian Noise Generator for Channel Code Evaluation
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...
CVPR
2000
IEEE
14 years 11 months ago
Statistical Modeling and Performance Characterization of a Real-Time Dual Camera Surveillance System
The engineering of computer vision systems that meet application speci c computational and accuracy requirements is crucial to the deployment of real-life computer vision systems....
Michael Greiffenhagen, Visvanathan Ramesh, Dorin C...
CODES
2007
IEEE
14 years 3 months ago
Combined approach to system level performance analysis of embedded systems
Compositional approaches to system-level performance analysis have shown great flexibility and scalability in the design of heterogeneous systems. These approaches often assume c...
Simon Künzli, Arne Hamann, Rolf Ernst, Lothar...
ASPDAC
2007
ACM
105views Hardware» more  ASPDAC 2007»
14 years 1 months ago
An Efficient Computation of Statistically Critical Sequential Paths Under Retiming
Abstract-- In this paper we present the Statistical Retimingbased Timing Analysis (SRTA) algorithm. The goal is to compute the timing slack distribution for the nodes in the timing...
Mongkol Ekpanyapong, Xin Zhao, Sung Kyu Lim