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» Performance Optimization and Evaluation for Linear Codes
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VEE
2010
ACM
218views Virtualization» more  VEE 2010»
14 years 2 months ago
Improving compiler-runtime separation with XIR
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
Ben Titzer, Thomas Würthinger, Doug Simon, Ma...
LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
ICS
2005
Tsinghua U.
14 years 1 months ago
Lightweight reference affinity analysis
Previous studies have shown that array regrouping and structure splitting significantly improve data locality. The most effective technique relies on profiling every access to eve...
Xipeng Shen, Yaoqing Gao, Chen Ding, Roch Archamba...
GECCO
2003
Springer
14 years 28 days ago
Quad Search and Hybrid Genetic Algorithms
A bit climber using a Gray encoding is guaranteed to converge to a global optimum in fewer than ¢¤£¦¥¨§© evaluations on unimodal 1-D functions and on multi-dimensional sph...
L. Darrell Whitley, Deon Garrett, Jean-Paul Watson
CODES
2004
IEEE
13 years 11 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan