50 search results - page 7 / 10 » Performance Portability on EARTH: A Case Study across Severa... |
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
PPOPP
2010
ACM
14 years 1 months ago
2010
ACM
To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical worklo...
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
DATAMINE
2000
13 years 6 months ago
2000
Data mining on large data warehouses is becoming increasingly important. In support of this trend, we consider a spectrum of architectural alternatives for coupling mining with da...
ICPP
2008
IEEE
14 years 1 months ago
2008
IEEE
—We address the recently recognized privatization problem in software transactional memory (STM) runtimes, and introduce the notion of partially visible reads (PVRs) to heuristic...