42 search results - page 6 / 9 » Performance and Configuration of Hierarchical Ring Networks ... |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Massive data transfer encountered in emerging multimedia embedded applications requires architecture allowing both highly distributed memory structure and multiprocessor computati...
LCN
2002
IEEE
14 years 13 days ago
2002
IEEE
A novel efficiency and effectiveness Internet multicast routing protocol is presented with short delay, high throughput, resource utilization and scalability for a single multicas...
ICPP
1993
IEEE
13 years 11 months ago
1993
IEEE
Scalability of parallel architectures is an interesting area of current research. Shared memory parallel programming is attractive stemming from its relative ease in transitioning...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...