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» Performance and Overhead in a Hybrid Reconfigurable Computer
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ICPP
2008
IEEE
14 years 1 months ago
Scalable Techniques for Transparent Privatization in Software Transactional Memory
—We address the recently recognized privatization problem in software transactional memory (STM) runtimes, and introduce the notion of partially visible reads (PVRs) to heuristic...
Virendra J. Marathe, Michael F. Spear, Michael L. ...
TVLSI
2010
13 years 2 months ago
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
Rupak Samanta, Jiang Hu, Peng Li
IEEEPACT
2009
IEEE
14 years 2 months ago
CPROB: Checkpoint Processing with Opportunistic Minimal Recovery
—CPR (Checkpoint Processing and Recovery) is a physical register management scheme that supports a larger instruction window and higher average IPC than conventional ROB-style re...
Andrew D. Hilton, Neeraj Eswaran, Amir Roth
SIGCOMM
1999
ACM
13 years 11 months ago
Load-Sensitive Routing of Long-Lived IP Flows
Internet service providers face a daunting challenge in provisioning network resources, due to the rapid growth of the Internet and wide fluctuations in the underlying traffic pa...
Anees Shaikh, Jennifer Rexford, Kang G. Shin
ASPLOS
2008
ACM
13 years 9 months ago
General and efficient locking without blocking
Standard concurrency control mechanisms offer a trade-off: Transactional memory approaches maximize concurrency, but suffer high overheads and cost for retrying in the case of act...
Yannis Smaragdakis, Anthony Kay, Reimer Behrends, ...