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TPDS
2010
93views more  TPDS 2010»
13 years 6 months ago
On the Interplay of Parallelization, Program Performance, and Energy Consumption
—This paper derives simple, yet fundamental formulas to describe the interplay between parallelism of an application, program performance, and energy consumption. Given the ratio...
Sangyeun Cho, Rami G. Melhem
LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
IPPS
1998
IEEE
13 years 12 months ago
A Mapping Methodology for Designing Software Task Pipelines for Embedded Signal Processing
Abstract. In this paper, we present a methodology for mapping an Embedded Signal Processing ESP application onto HPC platforms such that the throughput performance is maximized. Pr...
Myungho Lee, Wenheng Liu, Viktor K. Prasanna
ISPASS
2003
IEEE
14 years 27 days ago
Interplay of energy and performance for disk arrays running transaction processing workloads
The growth of business enterprises and the emergence of the Internet as a medium for data processing has led to a proliferation of applications that are server-centric. The power ...
Sudhanva Gurumurthi, Jianyong Zhang, Anand Sivasub...
MICRO
2005
IEEE
136views Hardware» more  MICRO 2005»
14 years 1 months ago
Automatic Thread Extraction with Decoupled Software Pipelining
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I...