157 search results - page 5 / 32 » Performance area efficiency in chip multiprocessors with mic... |
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
There are two basic models for the on-chip memory in CMP systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison o...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
Although silicon optical technology is still in its formative stages, and the more near-term application is chip-to-chip communication, rapid advances have been made in the develo...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
— An increasing number of hardware failures can be attributed to device reliability problems that cause partial system failure or shutdown. In this paper we propose a scheme for ...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...