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DAC
2010
ACM
13 years 9 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
CDC
2008
IEEE
149views Control Systems» more  CDC 2008»
13 years 11 months ago
Distributed computation under bit constraints
Abstract-- A network of nodes communicate via noisy channels. Each node has some real-valued initial measurement or message. The goal of each of the nodes is to acquire an estimate...
Ola Ayaso, Devavrat Shah, Munther A. Dahleh
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
14 years 3 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
DATE
2007
IEEE
113views Hardware» more  DATE 2007»
14 years 3 months ago
Congestion-controlled best-effort communication for networks-on-chip
Abstract. Congestion has negative effects on network performance. In this paper, a novel congestion control strategy is presented for Networks-on-Chip (NoC). For this purpose we in...
Jan Willem van den Brand, Calin Ciordas, Kees Goos...
ECRTS
2005
IEEE
14 years 2 months ago
Scheduling Tasks with Markov-Chain Based Constraints
Markov-Chain (MC) based constraints have been shown to be an effective QoS measure for a class of real-time systems, particularly those arising from control applications. Scheduli...
Donglin Liu, Xiaobo Sharon Hu, Michael D. Lemmon, ...