Sciweavers

1548 search results - page 290 / 310
» Performance evaluation and optimization of human control str...
Sort
View
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
14 years 4 months ago
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
GECCO
2007
Springer
159views Optimization» more  GECCO 2007»
14 years 4 months ago
Evolutionary hypernetwork models for aptamer-based cardiovascular disease diagnosis
We present a biology-inspired probabilistic graphical model, called the hypernetwork model, and its application to medical diagnosis of disease. The hypernetwork models are a way ...
JungWoo Ha, Jae-Hong Eom, Sung-Chun Kim, Byoung-Ta...
ICS
1998
Tsinghua U.
14 years 2 months ago
Data Prefetching for Software DSMs
In this paper we propose and evaluate the Adaptive++ technique, a novel runtime-only data prefetching strategy for software-based distributed shared-memory systems (software DSMs)...
Ricardo Bianchini, Raquel Pinto, Claudio Luis de A...
TVLSI
2008
107views more  TVLSI 2008»
13 years 10 months ago
Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs
Thermal hot spots and high temperature gradients degrade reliability and performance, and increase cooling costs and leakage power. In this paper, we explore the benefits of temper...
Ayse Kivilcim Coskun, T. T. Rosing, Keith Whisnant...
ISCA
2011
IEEE
258views Hardware» more  ISCA 2011»
13 years 2 months ago
A case for heterogeneous on-chip interconnects for CMPs
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. ...