121 search results - page 17 / 25 » Performance evaluation for system-on-chip architectures usin... |
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
ESTIMEDIA
2003
Springer
14 years 23 days ago
2003
Springer
— The constant increase in levels of integration and the reduction of the time-to-market have led to the definition of new methodologies stressing reuse. This involves not only ...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
SIGMETRICS
2005
ACM
14 years 1 months ago
2005
ACM
Wide-spread deployment of infrastructure WLANs has made Wi-Fi an integral part of today’s Internet access technology. Despite its crucial role in affecting end-to-end performan...