121 search results - page 5 / 25 » Performance evaluation for system-on-chip architectures usin... |
WOSP
2005
ACM
14 years 1 months ago
2005
ACM
Software performance based on performance models can be applied at early phases of the software development cycle to characterize the quantitative behavior of software systems. We...
LCTRTS
1998
Springer
13 years 11 months ago
1998
Springer
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
AAMAS
2006
Springer
13 years 7 months ago
2006
Springer
File Integrity Analyzers serve as a component of an Intrusion Detection environment by performing filesystem inspections to verify the content of security-critical files in order ...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
SDL
2003
13 years 9 months ago
2003
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...