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3DIC
2009
IEEE
169views Hardware» more  3DIC 2009»
14 years 20 days ago
3-D memory organization and performance analysis for multi-processor network-on-chip architecture
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid s...
Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerase...
ACMSE
2006
ACM
14 years 1 months ago
Mobility models for vehicular ad hoc network simulations
: There is a growing interest in deployment and evaluation of routing protocols for Vehicular Ad-Hoc Wireless Networks (VANETs) in urban contexts. The mobility model of nodes is on...
Niranjan Potnis, Atulya Mahajan
TON
2008
87views more  TON 2008»
13 years 7 months ago
Large-scale network parameter configuration using an on-line simulation framework
As the Internet infrastructure grows to support a variety of services, its legacy protocols are being overloaded with new functions such as traffic engineering. Today, operators en...
Tao Ye, Hema Tahilramani Kaur, Shivkumar Kalyanara...
JSS
2006
104views more  JSS 2006»
13 years 7 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
JDCTA
2010
104views more  JDCTA 2010»
13 years 2 months ago
Mean Shifts Identification Model in Bivariate Process Based on LS-SVM Pattern Recognizer
This study develops a least squares support vector machines (LS-SVM) based model for bivariate process to diagnose abnormal patterns of process mean vector, and to help identify a...
Zhi-Qiang Cheng, Yi-Zhong Ma, Jing Bu