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» Performance improvement with circuit-level speculation
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DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 1 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
ATAL
2004
Springer
14 years 23 days ago
Universality in Multi-Agent Systems
Much research in multi-agent systems reflects the field’s origins in classical artificial intelligence, showing how various refinements to the internal reasoning of individual a...
H. Van Dyke Parunak, Sven Brueckner, Robert Savit
SPATIALCOGNITION
2004
Springer
14 years 21 days ago
Characterizing Diagrams Produced by Individuals and Dyads
Diagrams are an effective means of conveying concrete, abstract or symbolic information about systems. Here, individuals or pairs of participants produced assembly instructions aft...
Julie Heiser, Barbara Tversky
ISCA
2002
IEEE
103views Hardware» more  ISCA 2002»
14 years 9 days ago
Efficient Dynamic Scheduling Through Tag Elimination
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
Dan Ernst, Todd M. Austin
MICRO
1999
IEEE
104views Hardware» more  MICRO 1999»
13 years 11 months ago
Control Independence in Trace Processors
Branch mispredictions are a major obstacle to exploiting instruction-level parallelism, at least in part because all instructions after a mispredicted branch are squashed. However...
Eric Rotenberg, James E. Smith