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» Performance improvement with circuit-level speculation
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ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 7 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
PODC
2009
ACM
14 years 8 months ago
Preventing versus curing: avoiding conflicts in transactional memories
Transactional memories are typically speculative and rely on contention managers to cure conflicts. This paper explores a complementary approach that prevents conflicts by schedul...
Aleksandar Dragojevic, Rachid Guerraoui, Anmol V. ...
IEEEPACT
2000
IEEE
13 years 11 months ago
On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors
In this paper, we look at two issues which could affect the performance of value prediction on wide-issue ILP processors. One is the large number of accesses to the value predicti...
Sang Jeong Lee, Pen-Chung Yew
PODC
1999
ACM
13 years 11 months ago
LOTEC: A Simple DSM Consistency Protocol for Nested Object Transactions
In this paper, we describe an e cient software-only Distributed Shared Memory (DSM) consistency protocol for an unconventional but important application domain - object transactio...
Peter C. J. Graham, Yahong Sui
IEEEPACT
2009
IEEE
13 years 5 months ago
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...