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ISCAS
2007
IEEE
99views Hardware» more  ISCAS 2007»
14 years 2 months ago
A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints
— Hermitian Codes offer desirable properties such as large code lengths, good error-correction at high code rates, etc. The main problem in making Hermitian codes practical is to...
Rachit Agarwal, Emanuel M. Popovici, Brendan O'Fly...
ISLPED
2006
ACM
73views Hardware» more  ISLPED 2006»
14 years 2 months ago
Substituting associative load queue with simple hash tables in out-of-order microprocessors
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...
Alok Garg, Fernando Castro, Michael C. Huang, Dani...
GIS
2006
ACM
13 years 8 months ago
Dynamic simplification and visualization of large maps
In this paper, we present an algorithm that performs simplification of large geographical maps through a novel use of graphics hardware. Given a map as a collection of non-interse...
Nabil H. Mustafa, Shankar Krishnan, Gokul Varadhan...
CIKM
2008
Springer
13 years 10 months ago
TinyLex: static n-gram index pruning with perfect recall
Inverted indexes using sequences of characters (n-grams) as terms provide an error-resilient and language-independent way to query for arbitrary substrings and perform approximate...
Derrick Coetzee
MICRO
2002
IEEE
173views Hardware» more  MICRO 2002»
14 years 1 months ago
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
Christoforos E. Kozyrakis, David A. Patterson