Computational complexity has been the primary challenge of many VLSI CAD applications. The emerging multicore and manycore microprocessors have the potential to offer scalable perf...
As the process technology enters the nanometer era, reliability has become a major concern in the design and manufacturing of VLSI circuits. In this paper we focus on one reliabil...
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Isma...
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
We propose Satisfiability Checking (SAT) techniques that lead to a consistent performance improvement of up to 3x over state-ofthe-art SAT solvers like Chaff on important problem ...
Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao ...