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» Performance of VLSI Engines for Lattice Computations
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PDCAT
2005
Springer
14 years 1 months ago
Optimal Routing in a Small-World Network
Recently a bulk of research [14, 5, 15, 9] has been done on the modelling of the smallworld phenomenon, which has been shown to be pervasive in social and nature networks, and eng...
Jianyang Zeng, Wen-Jing Hsu
DAC
2009
ACM
14 years 9 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
DAC
2004
ACM
14 years 8 months ago
Efficient power/ground network analysis for power integrity-driven design methodology
As technology advances, the metal width is decreasing with the length increasing, making the resistance along the power line increase substantially. Together with the nonlinear sc...
Su-Wei Wu, Yao-Wen Chang
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
14 years 1 months ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...
VLSID
2007
IEEE
149views VLSI» more  VLSID 2007»
14 years 8 months ago
Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes
Title of thesis: EFFICIENT AND ACCURATE STATISTICAL TIMING ANALYSIS FOR NON-LINEAR NON-GAUSSIAN VARIABILITY WITH INCREMENTAL ATTRIBUTES Ashish Dobhal, Master of Science, 2006 Thes...
Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava