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GLVLSI
2009
IEEE
155views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Buffer design and optimization for lut-based structured ASIC design styles
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu
GLVLSI
2005
IEEE
118views VLSI» more  GLVLSI 2005»
14 years 1 months ago
A continuous time markov decision process based on-chip buffer allocation methodology
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...
Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Dob...
CIKM
2010
Springer
13 years 6 months ago
StableBuffer: optimizing write performance for DBMS applications on flash devices
Flash devices have been widely used in embedded systems, laptop computers, and enterprise servers. However, the poor random writes have been an obstacle to running write-intensive...
Yu Li, Jianliang Xu, Byron Choi, Haibo Hu
ISLPED
2007
ACM
138views Hardware» more  ISLPED 2007»
13 years 9 months ago
Power optimal MTCMOS repeater insertion for global buses
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
Hanif Fatemi, Behnam Amelifard, Massoud Pedram
RSP
1998
IEEE
188views Control Systems» more  RSP 1998»
13 years 11 months ago
Performance and Interface Buffer Size Driven Behavioral Partitioning for Embedded Systems
One of the major differences in partitioning for codesign is in the way the communication cost is evaluated. Generally the size of the edge cut-set is used. When communication bet...
T.-C. Lin, Sadiq M. Sait, Walling R. Cyre