955 search results - page 18 / 191 » Performance optimization of multiple memory architectures fo... |
CSE
2009
IEEE
14 years 11 days ago
2009
IEEE
Sparse Matrix-Vector multiplication (SpMV) is a very challenging computational kernel, since its performance depends greatly on both the input matrix and the underlying architectur...
VLSISP
2008
13 years 8 months ago
2008
Many different video processor architectures exist. Its architecture gives a processor strength for a particular application. Hardwired logic yields the best performance/cost, but ...
IPPS
2006
IEEE
14 years 3 months ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
FPL
1998
Springer
14 years 1 months ago
1998
Springer
This paper discusses the memory interface of custom computing machines. We present a high speed parallel memory for the MoM-PDA machine, which is based on the Xputer paradigm. The ...
ISCAS
2007
IEEE
14 years 3 months ago
2007
IEEE
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...