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ASPLOS
1991
ACM
14 years 16 days ago
NUMA Policies and Their Relation to Memory Architecture
Multiprocessor memory reference traces provide a wealth of information on the behavior of parallel programs. We have used this information to explore the relationship between kern...
William J. Bolosky, Michael L. Scott, Robert P. Fi...
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 9 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
ISPAN
1997
IEEE
14 years 1 months ago
CASS: an efficient task management system for distributed memory architectures
The thesis of this research is that the task of exposing the parallelism in a given application should be left to the algorithm designer, who has intimate knowledge of the applica...
Jing-Chiou Liou, Michael A. Palis
CODES
2006
IEEE
14 years 3 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
ISCA
2012
IEEE
237views Hardware» more  ISCA 2012»
11 years 11 months ago
BOOM: Enabling mobile memory based low-power server DIMMs
To address the real-time processing needs of large and growing amounts of data, modern software increasingly uses main memory as the primary data store for critical information. T...
Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar...