955 search results - page 33 / 191 » Performance optimization of multiple memory architectures fo... |
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
Violations in memory references cause tremendous loss of productivity, catastrophic mission failures, loss of privacy and security, and much more. Software mechanisms to detect me...
ISCAPDCS
2004
13 years 10 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
DAC
2006
ACM
14 years 3 months ago
2006
ACM
Reduction of the on-chip memory size is a key issue in video codec system design. Because video codec applications involve complex algorithms that are both data-intensive and cont...
IJCAI
2003
13 years 10 months ago
2003
Sequence alignment is an important problem in computational biology. We compare two different approaches to the problem of optimally aligning two or more character strings: bounde...
MICRO
2003
IEEE
14 years 2 months ago
2003
IEEE
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...