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HIPC
2009
Springer
13 years 6 months ago
Integrating and optimizing transactional memory in a data mining middleware
As the size of available datasets in various domains is growing rapidly, there is an increasing need for scaling data mining implementations. Coupled with the current trends in co...
Vignesh T. Ravi, Gagan Agrawal
CSREAESA
2006
13 years 10 months ago
Static Program Partitioning for Embedded Processors
Modern processors have a small on-chip local memory for instructions. Usually it is in the form of a cache but in some cases it is an addressable memory. In the latter, the user is...
Bageshri Sathe, Uday P. Khedker
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
11 years 11 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
IFL
2001
Springer
146views Formal Methods» more  IFL 2001»
14 years 1 months ago
Optimizations on Array Skeletons in a Shared Memory Environment
Map- and fold-like skeletons are a suitable abstractions to guide parallel program execution in functional array processing. However, when it comes to achieving high performance, i...
Clemens Grelck
CASES
2005
ACM
13 years 11 months ago
Compilation techniques for energy reduction in horizontally partitioned cache architectures
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt