955 search results - page 46 / 191 » Performance optimization of multiple memory architectures fo... |
CASES
2003
ACM
14 years 2 months ago
2003
ACM
The proliferation of computing technology to low power domains such as hand–held devices has lead to increased interest in portable interface technologies, with particular inter...
ARC
2007
Springer
14 years 3 months ago
2007
Springer
Abstract. The novel design of high-speed and low-energy FPGA routing architecture consisting of appropriate wire segments and multiple Switch Boxes is introduced. For that purpose,...
ICASSP
2011
IEEE
13 years 24 days ago
2011
IEEE
Abstract—Widely distributed multiple radar architectures offer parameter estimation improvement for target localization. For a large number of radars, the achievable localization...
MICRO
1997
IEEE
14 years 1 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
SIPS
2006
IEEE
14 years 3 months ago
2006
IEEE
Abstract— This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signal processing algorithm...